Replacing SiO2 - Material and Processing Aspects of New Dielectrics

Replacing SiO2 - Material and Processing Aspects of New Dielectrics

S.De Gendt 1, C.Adelmann, A.Delabie, L.Nyns1, G.Pourtois, S.Van Elshocht

IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 1 also at KULeuven, Celestijnlaan 200F, B-3001 Leuven, Belgium

The paper aims at presenting a concise overview of some of the process development and material issues often encountered during the development of dielectric deposition processes for future high-k applications, and make you reminiscence of the past when ‘good old’ silicondioxide dominated the dielectric landscape.

Introduction

To increase CMOS performance, new materials are continuously being introduced. For logic technologies, high-k dielectrics and metal gates have been engineered successfully (1). Yet, new challenges are underway, as these high-k materials are considered as enabling technologies for advanced channel materials such as Ge and III-V materials. Also for future memory technologies, novel dielectric materials, with challenging CET/leakage specifications are required. Additionally, both for memory (trench capacitors) and logic (3D transistors), additional challenges are imposed on these materials, as suitable step coverage of the dielectric deposition processes is required (2). The move away from conventional SiO2 based dielectrics, and thus also from the thermal oxidation processes has opened pathways for physical vapor deposition (and controlled oxidation) or chemical vapor deposition processes to conquer the market for critical dielectric deposition processes. Once optimized processes are developed, likely identical material properties can be achieved for the same dielectric deposited by means of a variety of different deposition techniques. Yet, the pathway to these optimized processes is covered with challenging features, both intrinsic to the deposition process, to the nature of the dielectric or application. Obviously, one critical challenge deals with interface, interface passivation and control of the growth initiation. Atomic layer deposition is the ultimate technique to investigate the impact of dielectric film nucleation and growth as a function of surface preparation (i.e. active sites), crystal orientation (for 3D applications) and substrate (Si, Ge or III/V) dependency. Among the effects that need to be controlled are surface dependent film closure (for thin dielectric films), substrate inhibited or enhanced growth mechanisms, interfacial regrowth processes or passivation issues. Subsequently, also during the actual dielectric growth, challenges are numerous. For simple binary (i.e. metaloxide) compounds, the role of impurities and ‘dopant’ distribution (N-profile) are in the mean time well understood. However, when chemical vapor deposition processes are required to deposit ternary oxides (e.g. Hfsilicates, but also DyScOx or other permutations of the table of elements), solving the puzzle experimentally is challenging. During the actual growth process development, one has to account for differences in chemical reactivity – and thus growth – for the various elements (or precursors). Not the least, once incorporated in a dielectric stack, and exposed to subsequent thermal anneals, these films are observed to undergo crystallization, phase separation and phase mixing mechanisms,

ECS Transactions, 13 (2) 3-13 (2008)10.1149/1.2908610 © The Electrochemical Society

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which can significantly change the properties of these dielectrics to the better or the worse.

Experimental

Overview of deposition techniques The mere fact of switching from conventional SiO2 as gate dielectric of choice, implements a transition from conventional thermal oxidation processes of high purity semiconducting substrates towards deposition processes for alternative (metaloxide like) dielectrics. The latter deposition process is typically achieved by either physical or chemical deposition processes. An example of the application of physical deposition processes is given in Figure 1, whereby a metallic Hf layer is deposited on a substrate and subsequently oxidized in a controlled manner. Effective control of the oxidizing conditions (temperature and time) allows selectivity between stoechiometric HfO2 oxidation and formation of an interfacial SiO2 layer. More details can be found in [3] and papers cited therein. Despite the usefulness of this technique, chemical deposition techniques such as Metallo-organic Chemical Vapor deposition (MOCVD) and Atomic Layer Deposition (ALD), are considered as more mainstream techniques for controlled, conformal deposition of nanometer thin dielectric films.

Figure 1a: TEM micrographs representing the conversion of metallic Hf into HfO2, under controlled oxidation (CO) to minimize SiO2 formation.

Figure 1b: Visual representation of the difference in oxidation rate of Hf and Si and the process window for controlled oxidation.

Chemical Vapor Deposition (CVD) is a process whereby gaseous molecular precursors are converted to solid-state material on a heated surface. Gas species are introduced simultaneaously, whereby gas-phase reactions may create more reactive daughter products. These species can adsorb onto the wafer surface, causing desorption, surface diffusion or reaction causing a solid deposit (thin film). Very often metallo-organic (MO) precursors are being used for this CVD process. Like CVD, ALD is a chemical gas phase thin film deposition method. The distinct feature of ALD is that the film is grown through sequential saturative surface reactions that are realized by pulsing the two (or more) precursors into the reactor alternately, on at a time, separated by purging or evacuation steps. For ALD HfO2, HfCl4 is the preferred metal precursor while H2O has commonly been used as the oxidizing agent [4, 5]. It is obvious that for the CVD based processes,

ECS Transactions, 13 (2) 3-13 (2008)



chemical reactivity phenomena will have an influence on the quality of the films and these processes will be extensively discussed in the remainder of the paper. Experimental conditions All layers are deposited on 200mm p-type Si (100) wafers with a thin (~0.8-1.0 nm) SiO2 layer grown in an O3/H2O solution (IMEC-clean) and often referred to as a “chemical oxide” as starting surface, unless mentioned otherwise. For some selected experiments, also Ge substrates are employed. ALD is used for all initial growth studies and for all Hf-based dielectric layers. HfO2 is deposited in an ALCVDTM PULSAR® 2000 reactor, attached to a Polygon® 8200 platform. The PULSAR 2000 is a hot wall cross-flow type reactor. The pressure in the reactor is 1 torr. All depositions are performed at temperatures between 225 and 370°C with HfCl4 and H2O precursors. HfCl4 is a solid at room temperature. It is heated to approximately 185°C to achieve sufficient vapor pressure for the HfCl4 pulses. The H2O bubbler is kept at 18°C. The pulse times are varied from the standard pulse length (0.3 s) to several minutes. MOCVD is used for Dy2O3, Sc2O3, and DyxScyOz films, and these are deposited by Atomic Vapor Deposition (AVD®) on an AIXTRON Tricent® system with the TriJet® injector system using Dy(mmp)3 and Sc(mmp)3 as precursors in combination with O2. Both precursors are dissolved in toluene in a concentration of 0.1M with tetraglyme as stabilizer. AVD® introduces the precursors in a pulsed mode through separate, independent injectors. The deposition temperature is varied between 400 and 600°C and the reactor pressure is 1000 Pa. The thickness of the layers is measured by Spectroscopic Ellipsometry (SE) using a KLA/TENCOR ASET F5 that measures the optical response in the wavelength region between 193 and 800nm. A single layer model is used to determine the refractive index and thickness of the deposited layer (i.e. high-k layer and the interfacial layer (IL) in-between the high-k layer and the Si-substrate are measured as one layer). For a selected sample set, the SE thickness was verified by Transmission Electron Microscopy (TEM) and good correlation between both techniques is found. The composition of the different layers is determined by X-ray Photoelectron Spectroscopy (XPS) and Rutherford Backscattering Spectroscopy (RBS). XPS measurements are performed on a Theta300 system from Thermo Electron, using monochromated Al Ka photon (1486.6 eV). The energy resolution of the instrument is ~0.8 eV (FWHM of Si2p3/2 photoemission peak) and the binding energy calibration is made on the C1s peak positioned at 285.0 eV. Time of Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) profiles are measured with an IONTOF IV instrument. Both positive and negative ion profiles are measured using a 15 keV Ga beam for analysis and a 350 eV Xe beam for sputtering. Atomic Force Microscopy (AFM) measurements are done with a Dimension 3100 with a Nanoscope IV from Veeco in tapping mode using a etched single crystal silicon probe tip (TESP/RTESP) with a radius of curvature <10nm. The area sizes are 1x1 µm2 with a scan frequency of 0.5 - 0.7 Hz. TEM is performed on cross-sectional specimens in a Tecnai F30 (FEI) operating at 300kV. The samples are prepared by ion beam milling. Capacitors are processed using a Polysilicon encapsulated local oxidation (PELOX) isolation scheme and a TiN metal gate electrode. The layers used for electrical characterization receive a post deposition anneal in a low partial pressure O2 (0.5 Torr) at 800°C for 15s. CV- and IV-curves shown in this paper are measured after a forming gas anneal (FGA) at 520°C in a 5% H2 in N2 mixture at atmospheric pressure for 20 min.




The studied capacitor areas vary between 65x65 and 1000x1000 µm2. CV-curves are measured with a Keithley 4200 semiconductor characterization system at frequencies between 10 kHz and 1 MHz.

Results and Discussion

ALD dielectric film nucleation and growth Scientifically, atomic layer deposition is an ideal technique to explore – in an independent manner – the impact of dielectric film nucleation and growth as a function of surface preparation (i.e. active sites), crystal orientation (for 3D applications) and substrate (Si, Ge or III/V). In the following three sub-chapters the ALD dependency on these parameters will be discussed. Impact of surface preparation (i.e. active sites) [6]

Since ALD is a surface sensitive growth technique, optimization of the silicon surface

before HfO2 deposition is mandatory. By separating the precursor pulses, HfO2 growth will only occur through gas-substrate reactions and will be limited to the deposition of one monolayer per ALD cycle. However, a lack of available surface sites, initially present and afterwards formed after each reaction cycle, and/or steric hindrance of the adsorbed precursor molecules could cause saturation of these substrate reactions and subsequently limit the HfO2 deposition to less than a monolayer. Growing nanometer-thin HfO2 films by Atomic Layer Deposition (ALD) for implementation in advanced transistor structures is controlled by the density of reactive OH sites on the surface.

The impact of thin SiO2 starting surfaces, grown by wet chemical processes and by wetting a thermal oxide, on the nucleation and growth of ALD HfO2 has therefore been evaluated. Our results demonstrate that both surface pretreatments display the same dependence of the initial HfO2 growth on the interfacial layer thickness (see Figure 2a).

Figure 2a: Dependence of the HfO2 deposition (5 ALD cycles) on thickness of wet chemical and wetted thermal oxides.

Figure 2b: EOT-leakage scaling of ALD HfO2 on wet chemical as well as thermal oxides after wetting.

This correlation is first characterized by a linear increase, which can be interpreted in terms of increasing OH surface concentration. Once an certain ‘oxide thickness’ is reached (characterized by an ellipsometric oxide thickness of approximately 0.8 nm),




saturation of the HfO2 deposition occurs. Most likely, island like growth explains this behavior, i.e. the silicon substrate gets gradually covered by oxide, increasing the surface for hydroxyl termination. When the islands grow together into a closed layer, the surface will be completely covered by oxide and the number of reactive OH groups will be at a maximum, resulting in saturation of the HfO2 growth as is observed from an ellipsometric thickness of approximately 0.8 nm on. Steric hindrance of the adsorbed precursor molecules may also be responsible for limiting the HfO2 deposition, even before a closed oxide layer is obtained. However, since saturation occurs from the same oxide thickness on, irrespective of the reactor temperature, it is suggested that achieving a maximal OH density for the ALD process under consideration is saturating the HfO2 growth.

Despite the observation that the ALD deposition is independent on the kind of silicon surface pretreatment, differences in electrical behaviour are observed (Figure 2b). While both types of interfacial oxide show the same EOT-JG characteristics for initial SiO2 thicknesses above 0.8 nm, thinner wet chemical oxides result in low quality gate stacks when compared to the wetted thermal oxides for the same EOT, caused by regrowth of the chemical interfacial oxide. Etched thermal oxides seem to be more stable against Interfacial Oxide Thickness (IOT) regrowth, which is attributed to the improved quality of the thermally grown oxide layer. However, provided that the increase in IOT can be controlled, wet chemical oxides are expected to show more EOT downscaling potential.

Impact of crystal orientation (for 3D applications) [7] Emerging technologies such as FINFET transistors, but also memory applications

(trench capacitors) require excellent coverage of the high-k dielectric. This is one feature that is provided by Atomic Layer Deposition. However, as seen above, the HfO2 deposition using HfCl4/H2O is controlled by the OH surface density, it is important to evaluate for 3D applications if there would be an impact of the crystallographic orientation of the silicon substrate. It is known that the oxidation process does have a crystal orientation dependency; the (110) orientated substrate oxidizes faster than the (100) silicon. It is important to evaluate if this difference also affects the HfO2 nucleation.

Figure 3a: Dependence of the SiO2 thickness on the applied ozone concentration for both (100) and (110) orientated silicon.

Figure 3b: Initial HfO2 growth (5 cycles) as a function of the SiO2 thickness for O3/H2O wet chemical oxides on both (100) and (110) orientated silicon.

In this section, we demonstrate the impact of the crystallographic orientation of the

silicon substrate on both its oxidation and ALD HfO2 nucleation. During the wet chemical oxidation in O3/H2O, the (110) orientated silicon initially oxidizes faster than




the (100) silicon due to its higher surface atom density (Figure 3a). This difference in oxidation saturates once pure SiO2 is formed (self-limiting process). When considering the same SiO2 thickness, the substrate orientation does not influence the ALD growth of HfO2 (Figure 3b). Instead, this growth is mainly determined by the thickness of the SiO2 layer (i.e. OH coverage). It increases linearly with increasing thickness and saturates once the SiO2 thickness reaches approximately 0.4 nm. This observation states that the ALD HfO2 growth is independent of the silicon crystal orientation on the condition that the SiO2 starting surface is minimally 0.4 nm thick. For thicknesses below 0.4nm, a thicker HfO2 layer is obtained for the (110) silicon.

Impact of substrate (Si or Ge) [8] Germanium is a high performance device material due to its narrow band gap, high

mobility and low dopant activation temperatures. It has recently been put forth by the semiconductor industry as a potential replacement for planar silicon, which is unlikely to accommodate the severe scaling requirements for sub-45 nm transistor generations. However, a major technological drawback to the use of Ge is the difficulty in growing an insulating oxide comparable to SiO2 in Si technology. Deposited high-κ materials may provide a solution for the gate dielectric of Ge-based transistors.

Atomic Layer Deposition (ALD) is a suitable technique to deposit uniform films in the nanometer thickness range. In order to function as a gate dielectric, the layer should also be smooth and contain no holes. As the ALD growth behavior can depend on the substrate, it is important to investigate and compare the growth characteristics and morphology of the dielectric films on the specific substrates. At least two ALD growth characteristics are affected by the substrate. A first growth characteristic is the growth-per-cycle or growth rate, defined as the total amount of material deposited per reaction cycle. The growth-per-cycle can be expressed as thickness increment (nm) or as increase of areal density (number of atoms/nm2). A second growth characteristic influenced by the substrate is the growth mode, which refers to the way the deposited material is arranged on the substrate: the material can be deposited as islands, or in a more favorable case as a closed two-dimensional layer. On Ge, substrate enhanced HfO2 growth occurs: i.e. the growth-per-cycle is larger in the first reaction cycles than the steady growth-per-cycle of 0.04 nm. The enhanced growth goes together with island growth, indicating that more than a monolayer coverage of HfO2 is required for a closed film. A closed HfO2 layer is achieved after depositing 4 – 5 HfO2 monolayers, corresponding to about 25 ALD reaction cycles (Figure 4a) [8].




y = 1.111x + 12.16R2 = 0.9988

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Figure 4a: Hf coverage measured by RBS as a function of the number of ALD reaction cycles on HF cleaned Ge substrates.

Figure 4b: Cross sectional TEM images of a 12 and 200 cycles HfO2 layer deposited on HF cleaned Ge(100).

We have additionally demonstrated the atomic layer deposition of HfO2 on HF cleaned Ge substrates using HfCl4 and H2O precursors. According to this physical characterization study, the physical thickness of HfO2 dielectric layers grown on HF last Ge can be scaled down to about 1.6 nm. Optimization of the surface preparation resulting in a more two-dimensional growth mode may allow the further scaling of dielectrics layers to less than 1.6 nm. A second critical issue for the ultimate scaling of the Ge/high-κ stacks is the interfacial layer. A promising observation for HfO2 stacks deposited on HF cleaned Ge is that the bottom interfacial layer is less than 0.4 nm thin (Figure 4b). The scaling potential combined with the high mobility of the Ge substrate makes the Ge/high-κ stacks promising for high-performance CMOS applications. Deposition of ternary oxides

At present, Hf based dielectrics are among the most popular ones to replace SiO2. However pure HfO2 has been found to result in a degraded electron mobility in the Si channel, a significant threshold voltage (VT) shift (with polysilicon gates), and VT-instabilities (for thicker films), shifting attention towards HfSiOx. In the first subsection of this chapter, we will deal with growth aspects of HfSiOx based materials by ALD. Recently, rare earth oxide materials have been identified as potentially interesting alternative dielectrics also, since they present a k-value around 20. In addition, it has been shown that the bandgap is comparable to HfO2, so the gate leakage is expected to be comparable as well. In the second subsection of this chapter, we will discuss processing issues of rare earth oxides deposited by means of MOCVD.

Silicate processes [9] In this section, we study the Atomic Layer Deposition (ALD) of hafnium silicate gate

dielectrics from HfCl4, SiCl4 and H2O. The proposed reaction sequences for HfO2 and SiO2 ALD are the same:

y X-OH + XCl4 → (X-O)y-XCl(4-y) + y HCl X-Cl + H2O → X-OH + HCl




The surface species are underlined, X = Hf or Si and y is the number of OH surface

sites reaction per XCl4. HfCl4/H2O ALD has a broad process window with deposition temperatures between 180 and 600°C. On the other hand, the ALD of SiO2 from SiCl4/H2O occurs only at temperatures higher than 327°C with very large SiCl4 exposures (> 109 Langmuirs, (1 L = 10-6 torr s)). The SiO2 film growth is controlled mainly by the low reaction rate of the SiCl4 half-reaction.

Experimentally, it was shown that SiCl4 quickly reacts with surface sites formed by the HfCl4/H2O reactions. The chemisorption on sites introduced by the SiCl4/H2O reactions is much slower and requires excessive SiCl4 doses. Hf-OH and Si-OH surface sites react differently with SiCl4 and HfCl4. The chemisorption of SiCl4 and HfCl4 on both types of surface sites was investigated by first-principle simulations. The surface sites were modeled using (OH)3-Si-OH and (OH)3-Hf-OH clusters (Figure 5). The ligand exchange reactions of HfCl4 and SiCl4 on Si-OH and Hf-OH are all exoenergetic with reaction enthalpies between -13 and -20 kcal/mol. Thus, all reactions are accessible from a thermodynamic point of view. However, there are differences in the energy barriers required to form the activated complexes. HfCl4 forms a stable complex with both kinds of surface sites through a Lewis acid/base interaction between the oxygen lone pair electrons and the empty d-orbitals of hafnium. The complex is more stable for the Hf-OH site than for Si-OH due to a weak electrostatic interaction between the Cl ligand and the Hf atom of the surface. On the other hand, SiCl4 does not easily adsorb on the Si-OH and Hf-OH sites. The SiCl4 chemisorption on Hf-OH proceeds with a modest energy barrier (4 kcal/mol). The calculated energy barrier for chemisorption on Si-OH is much larger (15 kcal/mol). The energy barrier arises from the necessity of the SiCl4 molecules to form a sigma bond with the oxygen atom of the -OH sites. The barrier is reduced in presence of Hf-OH sites due to favorable electrostatic interactions. Thus, the energy barrier required to form the activated complex makes the chemisorption of SiCl4 on Si-OH sites kinetically much slower than on Hf-OH sites. The modeling results also reveal differences in the hydrolysis mechanism of Si-Cl and Hf-Cl bonds [9]. Si-Cl bonds are more difficult to hydrolyze. Consequently, a long H2O exposure is beneficial for the hydrolysis of the Si-Cl bonds.

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Figure 1a: Reaction path computed for HfCl4 reacting with a Hf-OH (dashed line) and a Si-OH (continuous line) site. TS

Figure 2b: Reaction path computed for SiCl4 reacting with a Hf-OH (dashed line) and a Si-OH (continuous line) site. TS




indicates the transition state. indicates the transition state. Complex rare earth oxides [10, 11] Alternative materials such as rare earth based dielectrics are of interest to obtain

proper threshold voltages as well as to engineer a material with a high thermal stability. We have studied rare earth based dielectrics such as Dy2O3, DyHfOx, DyScOx, La2O3, HfLaOx, and LaAlOx. A typical and frequently described phenomenon observed for rare earth oxides is silicate formation that can occur when a rare earth (oxide) is in contact with a Si-containing dielectric or a silicon substrate in the presence of oxygen. As such, it has been used to consume the typical SiO2-like interfacial between high-k and silicon substrate or to boost its k-value. The extent of this silicate formation depends on parameters such as temperature and the ion radius of the rare earth element. As these rare earth silicates form and hence are stable at high temperatures, they are an interesting alternative for hafnium silicates that have been reported to phase separate when annealed at high temperatures.

When we consider ternary rare earth dielectrics, a different behavior can be observed

not only depending on the ratio of the rare earth element present, but also depending on the actual element that is combined with the rare earth element, e.g. HfLaOx vs LaAlOx. In Figure 7a, we have plotted the normalized thickness increase measured after a total anneal 120s in O2 as function of composition for ternary oxides of Dy (mixed with Hf or Sc) and La (mixed with Hf or Al). From Figure 7a, it can be clearly seen that the thickness increase for ternary rare earth based oxides is not a linear relation as function of composition. When we consider for example DyScOx layers with different compositions, then we observe that increasing the content of the rare earth element does not result in a gradual increase of the silicate formation. To the contrary, a rather steep increase in silicate formation is observed between ~25 and ~50% of Dy (nominal composition). A very similar behavior is observed for HfLaOx that also demonstrates a rather steep increase in silicate formation somewhere between 14 and 27% La (XPS-determined composition). A slightly different observation is made for DyHfOx where also a steep increase is observed, but in this case at a much larger Dy-content as compared to DyScOx, i.e. in the presence of Hf a very large amount of Dy is needed for silicate formation to occur suggesting that Hf is more efficient in suppressing silicate formation for Dy2O3 as compared to Sc. For LaAlOx on the other hand, a thickness increase is observed already starting at very low La-concentrations indicating not only that Al has hardly any effect on the La-induced silicate formation, but also that very small amounts of La are sufficient to initiate silicate formation.




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Figure 7a: Normalized thickness increase as function of composition for HfLaOx, LaAlOx, DyHfOx, and DyScOx. Solid and dashed lines are a guide to the eye for La and Dy-containing layers, respectively.

Figure 7b: TEM of a 12nm Dy2O3 layer deposited on 20nm SiO2 after a 60s 1000°C N2 anneal. Consumption of the SiO2 layer results in amorphization by formation of a DySiOx layer.

The silicate formation described above is an additional parameter to take into account

when studying crystallization behavior of rare earth containing layers. Indeed, when the Si-content increases as a result of the silicate formation, it raises the crystallization onset temperature keeping the layer amorphous up to higher temperatures. As a simple example to illustrate this we show in Figure 7b a cross-section TEM of a 12 nm Dy2O3 layer deposited on 20nm SiO2 after annealing at 1000°C for 60s in a N2 ambient. While Dy2O3 is already crystalline as-deposited, a large part of the Dy2O3 is seen to be amorphous after anneal. This is obviously the result of amorphization that occurred during anneal because of silicate formation with the thick SiO2 layer underneath and consuming it in the process (the SiO2 layer is 5 nm thinner after anneal). For the present stack and anneal conditions 6 nm Dy2O3 is transformed into a DySiOx and ~5nm crystalline Dy2O3 is left on top. More aggressive anneal conditions or a thinner Dy2O3 would have resulted in a fully amorphous layer. Since XRD cannot distinguish if an increase in crystallization temperature is the result of the material itself or because of silicate formation for that specific composition, the crystallization temperature of a material can be overestimated. When not carefully taking into account silicate formation that can potentially occur depending on the process conditions and the layer underneath, e.g. a SiO2 layer is often used as starting surface for the deposition of high-k layers.

Conclusions

Scaling of CMOS technology requires the introduction of a wide range of new materials and deposition techniques. Especially the area of dielectric processes is prone to many changes, not the least the switch from thermal oxidation based dielectrics to chemically deposited dielectrics. These dielectrics are being considered for both planar and non-planar (3D) features, for deposition on Si and other semiconducting substrates, and for material of complex composition (i.e. binary and ternary metal oxides). Through a few examples, the complexity and attention points for this process are being highlighted.




Acknowledgements The authors would like to thank IMEC’s Industrial Affiliation Program for advanced CMOS technology and the partners therein for providing the necessary funding for this research. Also IMEC’s pline, thin film deposition and characterization groups are gratefully acknowledged for support and fruitful discussions.

References

1. www.intel.com/technology/silicon/45nm_technology.htm 2. ITRS roadmap, http://www.itrs.net/links/2007ITRS/Home2007.htm. 3. K.Yamamoto et al, IEEE Trans. On Elect.Dev., 53(5), 1153, 2006. 4. M. Ritala and M. Leskelä, in Handbook of Thin Film Materials, Vol. 1, N.S.

Nalwa, Editor, p. 103, Academic, San Diego (2002). 5. R. L. Puurunen, J. Appl. Phys., 97 (12), 121301, 2005. 6. L. Nyns, et al, J. Electrochem.Soc., 153(9), F2005, 2006. 7. L.Nyns, et al, ECS Trans., 11(4), 73, 2007. 8. A.Delabie et al, J.Appl.Phys., 97(6), 064104, 2005. 9. A.Delabie et al, J.Vac.Sci.Technol.A, 25(4), 1302, 2007. 10. S.Van Elshocht et al, J.Vac.Sci.Technol.A, 26(4), 1302, 2008. 11. C.Adelmann et al, Appl.Phys.Lett., accepted for publication 2008.




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Replacing SiO2 - Material and Processing Aspects of New Dielectrics

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