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Microelectronic Engineering 84 (2007) 2511–2516

Ni–Pt silicide formation through Ti mediating layers

Paul Besser a,b,*, Christian Lavoie b, Ahmet Ozcan c, Conal Murray b,Jay Strane c, Keith Wong c, Michael Gribelyuk c, Yun-Yu Wang c,

Christopher Parks c, Jean Jordan-Sweet b

a Technology Research Group, Advanced Micro Devices, Inc., Sunnyvale, CA, USAb IBM T.J. Watson Research Center, Yorktown Heights, NY, USA

c IBM Semiconductor Research and Development Center, Hopewell Junction, NY, USA

Received 5 May 2007; accepted 7 June 2007Available online 14 June 2007

Abstract

With Ni1�xPtxSi, the variation in queue time between the final surface cleaning and Ni–Pt deposition represents a significant manu-facturability issue. A short queue time is often difficult to maintain, leading to the formation of an oxide layer on the Si substrate prior toNi–Pt deposition that can affect the formation of Ni1�xPtxSi and its texture. In this manuscript, it will be shown that an extended queuetime prior to Ni–Pt deposition leads to morphological changes in the Ni1�xPtxSi formation sequence. A layer of Ti deposited betweenNi–Pt and Si reduces the native oxide and may facilitate Ni1�xPtxSi formation. With increasing Ti thickness, the presence of metal-richphases is gradually reduced and the formation temperature of Ni1�xPtxSi increases, suggesting a direct formation of Ni1�xPtxSi from Ni–Pt. In the presence of an interfacial oxide, an increase in formation temperature is also observed with increasing Ti interlayer thickness.When the Ti layer is sufficiently thick, the phase formation sequence becomes relatively insensitive to the presence of an interfacial oxideor extended queue time.� 2007 Elsevier B.V. All rights reserved.

Keywords: Nickel silicide; Titanium; Oxidation; Mediated reaction

1. Introduction

Cobalt silicide has exhibited extendibility challenges,such as incompatibility with Si–Ge integration schemes,voiding on narrow linewidths and unavoidable roughness[1–8]. As a result, nickel silicide (NiSi) was evaluated forthe 90 nm technology node and beyond [9–11]. AlthoughNiSi resolves the shrinking gate CD problem that accom-panies scaling and forms a low resistance silicide on SiGesubstrates, its implementation on SOI substrates is difficultbecause of the low morphological stability and challengesrelated to integration [4,6,12–14]. The incorporation of Pt

0167-9317/$ - see front matter � 2007 Elsevier B.V. All rights reserved.doi:10.1016/j.mee.2007.06.003

* Corresponding author. Address: Technology Research Group, Ad-vanced Micro Devices, Inc., Sunnyvale, CA, USA. Tel.: +1 408 749 2350;fax: +1 408 774 7499.

E-mail address: paul.besser@amd.com (P. Besser).

into NiSi thin films was shown to delay both the agglomer-ation of NiSi and the formation of NiSi2 [15–18]. Recently,it has been established that the demanding integrationrequirements are satisfied for implementation into high-performance 90 and 65 nm SOI technologies, and NiPtSiis now in volume production at 65 nm [14].

An important manufacturability issue is the variation inqueue time between the pre-clean and Ni deposition. Shortqueue times are difficult to maintain leading to the forma-tion of an oxide layer on the Si prior to Ni–Pt deposition.The effect of Ti capping layers on pure Ni films has beeninvestigated to mitigate oxidation of the underlying metalfilms prior to silicidation [19,20]. Ti acts as a getteringagent which, during the annealing, can diffuse to themetal/Si interface. Because the formation enthalpy of TiOx

is greater than that of SiO2, Ti at the interface reduces thesurface oxide [21]. The use of an intermediate Ti layer

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between a pure Ni layer and Si substrate has also beenstudied [22]. For very thick Ti films (>10 nm), a NiTi3phase has been reported, below which nickel silicide forms.For Ti films of approximately 2–3 nm, Ni diffusion isdelayed as the Ti layer acts as a diffusion barrier so thatthe predominant silicide phase formed is the Si-rich NiSi2for moderate annealing conditions (350 �C, 30 s.) [23,24].The NiSi2 morphology consisted of pyramid-shaped struc-tures pointing downward into the Si. As the Ti layer thick-ness decreases, the extent of mediated epitaxy and theuniformity of the Ti film both decrease. In this manuscript,we investigate the formation of NiPtSi through a Ti medi-ating layer, with and without the presence of an extra SiO2

layer at the Si surface.

2. Experimental

Prior to metal deposition, the Si (100) SOI substrateswere cleaned with dilute hydrofluoric acid (dHF). Follow-ing the acid cleaning, metallic stacks were sputter-depositedwithout breaking vacuum using DC magnetron, physicalvapor deposition (PVD) under ultra-high vacuum condi-tions. The metal stacks consisted of 0–2 nm of Ti followedby 10 nm of Ni–Pt followed by a thin TiN capping layer.On some wafers, a SiO2 layer was grown between the Sisubstrate and the deposited metal by either a deionized(DI) water soak (hours) or an extended queue time (manyhours). On other wafers, the samples had a very shortqueue time (minutes) between dHF clean and metaldeposition.

Annealing experiments to observe phase formationsequences were performed at the National SynchrotronLight Source (NSLS) X20C beam line at BrookhavenNational Laboratory (New York, USA) where the forma-tion of sequential phases is followed in situ by the develop-

Fig. 1. Quad-SIMS depth profiles for as deposited Ni–Pt on SOI (without Ti laPt deposition. Note the oxygen at the NiPt/NiPtSi interface with the long que

ment of their characteristic diffraction patterns [1,25–27].Annealing is performed in a purified and inert atmosphereand the temperature measurements, calibrated usingmetal–silicon eutectics, are precise to ±3 �C. For theX-ray diffraction (XRD), we selected an energy of6.9 keV (k = 0.18 nm) at which the incident X-ray flux isgreater than 1013 photons/s. Unless otherwise specified,the X-ray beam was incident at an angle of 27� from theplane of the sample. This incidence angle was selected toallow a near Bragg–Brentano geometry for characteristicX-ray diffraction peaks from all important phases in theNi–Si system within the 2h window of the linear positionsensitive detector. In the current configuration, a diffrac-tion curve (covering a range of 2h angles of up to 14�) froma �10 nm metal film can be acquired in less than 100 ms.This set-up allows for real time monitoring of phase forma-tion at temperature ramp rates of up to 50 �C/s and at tem-peratures up to 1100 �C. Additional annealing experimentswere performed in an ambient-controlled, commerciallyavailable rapid thermal anneal tool (AG Associates). Ex

situ analyses were performed on the wafers using a quadru-pole Secondary Ion Mass Spectroscopy (SIMS) depth-probe analysis for Pt, Ni and O profiles and cross-sectionalScanning Transmission Electron Microscopy (XSTEM)analysis.

3. Results and discussion

In order to quantify the Ni–Pt/Si interface for as depos-ited Ni–Pt on SOI (without Ti layer), Quad SIMS (Fig. 1)was performed on samples with a short and long queuetime. The SIMS plots indicate the presence of a Ni–Pt–Siintermixing layer upon deposition. SIMS revealed elevatedO levels at the Ni–Pt/NiPtSi interface for samples with thelonger queue time, indicative of Si oxidation prior to metal

yer) for a short (left) queue time and a long (right) queue time prior to Ni–ue time, indicated by arrow on the figure at right.

P. Besser et al. / Microelectronic Engineering 84 (2007) 2511–2516 2513

deposition. The presence of this oxide layer was shown incertain conditions to directly affect yield. Fig. 2 shows theSRAM yield of a 65 nm logic microprocessor as a functionof wafer number. While these wafers contain other processvariations that can affect yield, the dominant factor in thiscase was the queue time. The long queue time on the righthad significantly degraded yield compared to the shortqueue time (left).

Using the in situ XRD apparatus, the effect of Si oxidethickness on the metal/Si reaction was investigated.Fig. 3 illustrates the variation in phase formation tempera-ture and phase texture (grain orientation) for 10 nm Ni–Ptdeposited onto SOI Si substrates under three conditions: ashort queue time, a long queue time and a DI water soak(3 h). The texture of the Ni–Pt, as evidenced by the changein intensity of the Ni peak at �52� is altered both by thelong queue time and the water soak. In general for thinmetal films, deposition on SiO2 (vs. Si(10 0) substrates)leads to films that show weaker textures (more randomgrain orientations). In addition, the texture of the metal-rich silicides (53� and 56�) and the NiSi (49� and 54�) areaffected by the presence of the contamination (oxide) layerbetween the metal and Si. While the texture of the NiSi is

Fig. 2. SRAM device yield for wafers with a short (left) and a long (right)queue time prior to Ni–Pt deposition. The yield is degraded with longqueue times.

Fig. 3. Phase formation sequence for Ni–Pt during annealing for a short (left)Ni–Pt deposition.

similar for both of the samples with interfacial oxides(queue time and soak), the water soak sample showedlower XRD intensities for the metal-rich region.

Quad-SIMS depth profiles (Fig. 4) were collected after aNi–Pt formation anneal to 450 �C for Ni–Pt on SOI (with-out Ti layer) for a short and a long (right) queue time.These depth profiles reveal an oxygen peak above the sili-cide, at the TiN cap/Ni1�xPtxSi interface for samples withthe long queue time, confirming both the oxidation prior tometal deposition and that the metals are the primary diffu-sion species even with this oxide. In addition, the Pt levelnear the Ni1�xPtxSi/Si interface is lower with a long queuetime, suggesting that Pt diffusion is suppressed by the oxidelayer at the interface.

A layer of Ti deposited between Ni–Pt and Si reducesthe native oxide (and incorporates OA and SiA into solidsolution) and may facilitate Ni1�xPtxSi formation. Fig. 5highlights the effect of a 2 nm Ti interlayer on the Ni–Pt phase formation sequence. When the Ti layer is suffi-ciently thick, the phase formation sequence becomes rela-tively independent of interfacial oxide, and the processbecomes insensitive to the DI water soak. In addition,the Ti layer increases the temperature at which Ni1�xPtxSiforms, and the metal-rich phases are not observed. TheNi1�xPtxSi may form directly from Ni–Pt albeit at ahigher temperature. This increase in formation tempera-ture is clearly observed in Fig. 6 for increasing Ti inter-layer thickness in the presence of interfacial oxide. Nimust diffuse through the Ti layer to form NiPtSi, and ahigher thermal budget is required with increased Ti thick-ness. In addition, the NiPt peak is more stable both intemperature and in 2h angle as the shift towards higherangle before disappearance is eliminated with thicker Tiinterlayer.

Fig. 7 quantifies the empirical observations of the previ-ous section. The temperatures at which the Ni peak disap-pears and NiSi peak appears are presented as a function ofTi interlayer thickness, with and without a water soak.Higher temperatures are required to form the low resis-tance Ni1�xPtxSi phase with increasing Ti thickness. Inaddition, NiPt deposited on Si with a DI water soakrequires higher temperatures to form the low resistance

queue time, a long (middle) queue time, and a water soak (right) prior to

Fig. 4. Quad-SIMS depth profiles for Ni–Pt on SOI (without Ti layer) for a short (left) queue time and a long (right) queue time after the Ni–Pt formationanneal. Note the lower Pt level near the NiPtSi/Si interface and the oxygen peak at the TiN/NiPtSi interface with the long queue time, indicated by arrowson the figure at right.

Fig. 5. Ni–Pt–Si formation under four conditions: after DHF with short queue time (top) and water soak (bottom), and without (left) and with (right) a Tiinterlayer between the Si and Ni–Pt.

Fig. 6. Ni–Pt phase formation sequences with an oxide between the Ni–Pt and Si. The Ti interlayer thickness varies from 0.5 to 2 nm.

2514 P. Besser et al. / Microelectronic Engineering 84 (2007) 2511–2516

250

300

350

400

450

500

0 0.5 1 1.5 2 2.5

Ti Thickness (nm)

Tem

per

atu

re (

C)

Ni peak disappear- no soak

NiSi peak appear - no soak

Ni peak disappear - soak

NiSi peak appear - soak

Fig. 7. Temperature of Ni diffraction peak disappearance and NiSiformation as a function of Ti interlayer thickness, with and without awater soak. The temperature delta between Ni diffraction peak disap-pearance and NiSi formation corresponds to the temperature range overwhich the metal-rich phases are present.

P. Besser et al. / Microelectronic Engineering 84 (2007) 2511–2516 2515

phase than NiPt deposited on bare Si (short queue time).This figure demonstrates that Ni1�xPtxSi formation tem-perature increases by �50 �C for every 0.5 nm of Ti depos-ited between the NiPt and Si. The temperature increase isrelatively independent of the oxide layer, but the absolutetemperature of silicide formation is higher with the oxidelayer present at the interface.

As was observed earlier with the reaction of pure Niwith Si, the presence of a Ti interlayer may lead to veryrough interfaces. With the thickest Ti layers studied here,we observed the formation of a rough and partially fac-etted interface (Fig. 8). While the silicide phases at theinterface have not been locally identified, some of thefacets suggest possible formation of the disilicide phase.As Pt is particularly efficient in retarding the disilicideformation (PtSi2 does not exist under equilibrium condi-tions), this result may suggest that very little Pt canreach the interface and prevent formation of this rough

Fig. 8. Cross section TEM of Ni–Pt silicide in the presence of a 2 nm Ti inte

disilicide phase. Alternately, non-uniformity in the diffu-sion barrier may lead to a non-uniform monosilicide.In terms of process window for devices, the interfacecan only suffer a limited roughening before some levelof device degradation is observed. As a result, the opti-mal Ti interlayer thickness is a compromise between sen-sitivity to Si surface preparation and the interfacialroughness appearing with thicker Ti interlayers.

4. Conclusions

An extended queue time prior to NiPt deposition leadsto changes in the Ni1�xPtxSi formation characteristics. ATi layer deposited between Ni–Pt and Si reduces the nativeoxide and may facilitate Ni1�xPtxSi formation. Asexpected, the presence of this Ti interfacial layer affectsthe phase formation sequence: the Ti interlayer eliminatesthe presence of metal-rich phases and increases the temper-ature at which Ni1�xPtxSi forms. For thicker interlayers,Ni1�xPtxSi may form directly from Ni–Pt. In the presenceof interfacial oxide, an increase in formation temperature isalso observed with increasing Ti interlayer thickness. Whenthe Ti layer is sufficiently thick, the phase formationsequence becomes relatively insensitive to variations inqueue time before deposition, and the process becomesinsensitive to the presence of an interfacial oxide orextended queue time. SIMS data show that more Ptremains near the surface of the silicide suggesting that thePt is more efficiently blocked by the Ti/oxide layer. Withthicker Ti interlayers, a large roughening of the silicide/sil-icon interface is observed. The reduction in sensitivity tosurface preparation using Ti interlayers must be carefullyoptimized as to not degrade device performance.

Acknowledgments

The synchrotron measurements were performed at theNational Synchrotron Light Source (NSLS). Use of NSLS,Brookhaven National Laboratory, was supported by theUS Department of Energy, Office of Science, Office of

rlayer. The Si/Silicide interface shows significant roughness and faceting.

2516 P. Besser et al. / Microelectronic Engineering 84 (2007) 2511–2516

Basic Energy Sciences, under contract No. DE-AC02-98CH10886. We thank Andy Turansky for assistance withmeasurements.

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